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This article is part of the series CMOS RF Circuits for Wireless Applications.

Open Access Open Badges Research Article

Design and Characterization of a 5.2 GHz/2.4 GHz Fractional- Frequency Synthesizer for Low-Phase Noise Performance

John WM Rogers1*, Foster F Dai2, Calvin Plett1 and MarkS Cavin3

Author Affiliations

1 Carleton University, 1125 Colonel Drive Ottawa, ON, Canada, K1S 5B6

2 Electrical and Computer Engineering Department, Auburn University, Auburn, AL 36849-5201, USA

3 Alereon, Inc., 7600 North Capital of Texas Highway, Building C, Suite 200 Austin, TX 78731, USA

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EURASIP Journal on Wireless Communications and Networking 2006, 2006:048489  doi:10.1155/WCN/2006/48489

The electronic version of this article is the complete one and can be found online at: http://jwcn.eurasipjournals.com/content/2006/1/048489

Received:8 August 2005
Revisions received:8 January 2006
Accepted:13 January 2006
Published:15 March 2006

© 2006 Rogers et al.

This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

This paper presents a complete noise analysis of a -based fractional- phase-locked loop (PLL) based frequency synthesizer. Rigorous analytical and empirical formulas have been given to model various phase noise sources and spurious components and to predict their impact on the overall synthesizer noise performance. These formulas have been applied to an integrated multiband WLAN frequency synthesizer RFIC to demonstrate noise minimization through judicious choice of loop parameters. Finally, predicted and measured phase jitter showed good agreement. For an LO frequency of 4.3 GHz, predicted and measured phase noise was rms and rms, respectively.


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